Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, in particular to a NAND-type flash memory.
Description of the Related Art
As an electrically erasable programmable and highly scalable nonvolatile semiconductor memory device (EEPROM), a NAND-type flash memory has been known. The NAND-type flash memory includes a plurality of memory cells serially connected in such a form that adjacent ones share a source/drain diffused layer to configure a NAND cell unit. Both ends of the NAND cell unit are connected to a bit line and a source line via respective selection gate transistors. Such the configuration of the NAND cell unit makes it possible to achieve a smaller unit cell area and larger capacity storage than that of the NOR-type.
The memory cell in the NAND-type flash memory includes a charge storage layer (floating gate) formed on a semiconductor substrate with a tunnel insulator film interposed therebetween, and a control gate stacked thereon with an inter-gate insulator film interposed therebetween, thereby storing data nonvolatilely in accordance with a charge storage state of the floating gate. Specifically, for example, a high threshold voltage state resulted from injection of electrons into the floating gate is defined as data “0”, a low threshold voltage state resulted from release of electrons from the floating gate is defined as data “1”, and the memory cell stores binary data. Recently, a program threshold distribution is fragmented to achieve multi-valued storage such as four-valued storage.
The fine fabrication of the flash memory and the fragmentation of the program threshold distribution cause the following problems.
Firstly, as for a memory cell adjacent to the selection gate transistor, electrons are injected into the floating gate under the influence of the gate-induced drain leakage current GIDL (Gate-Induced Drain Leakage), and therefore failed write is caused easily.
Secondly, the shorter the distance between memory cells are, the stronger the interference between adjacent cells becomes, for example. This is because scaling in the longitudinal direction is more difficult than the reduction by scaling in the lateral direction in the cell array.
More specifically, the floating gate of the memory cell is capacitively coupled to the control gate (word line) located above and to the substrate (channel) located immediately beneath. When cells are fine-fabricated, the capacity between the floating gate of one memory cell and the floating gate of a memory cell adjacent thereto increases relative to the capacity between the floating gate and the control gate and substrate. The inter-cell interference based on the capacitive coupling between the floating gates of the adjacent cells exerts an influence on the threshold of the already data-programmed memory cell so that the threshold is shifted in accordance with the threshold fluctuation of a memory cell to be data-programmed later.
As for the first problem, a dummy cell not for use in data storage may be arranged adjacent to the selection gate transistor. Such a system is effective to a certain extent (see, for example, Patent Document 1: JP 2004-127346A).
Memory cells for multi-valued storage may be used to achieve a larger capacity while memory cells for binary storage may be used only as memory cells on both ends of a memory string adjacent to the selection gate transistors to provide the threshold distribution with a margin, thereby improving the reliability as in a technology proposed (Non-Patent Document 1: “16-Gigabit, 8-level NAND Flash Memory with 51 nm 44-Cell String Technology”, Tae-Kyung Kim, et al. Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European).
These measures, however, cannot solve the second problem. In particular, in the case of the structure as in Non-Patent Document 1, the number of program stages for the memory cells on both ends of the memory string is lower than the number of program stages for other memory cells. Therefore, it is difficult to recover the fluctuation of the threshold distribution caused by the inter-cell interference from the adjacent memory cell as a problem.